The present invention relates to a new memory structure for use in high density memory chips. In particular, the present invention provides a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate. The present invention also includes a new NVRAM cell structure. Additionally, the present invention relates to processes for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and processes for forming a new NVRAM cell structure.
Laser fusible redundancy technology plays a key role for improving the yield of today""s high density memory chips. However, disadvantages exist associated with such technology. For example, devices produced according to the technology are bulky and costly in terms of chip area. The fuse blowing process that may occur in devices according to this technology may damage adjacent devices. The fuse blowing process is time consuming and unreliable, and the fuses are not reprogrammable.
As memory circuits become more sophisticated, it is often necessary to incorporate a block of EEPROM into other memory arrays, such as DRAM or SRAM. One example of such a device is a xe2x80x9csmart cardxe2x80x9d. In a smart card, RAM serves as a scratch pad, ROM stores programs and runs the cards operating system, EEPROM includes user data, and a microcontroller allocates the memory and runs an encryption program. One example of a smart card is described in John Gallant, Smart Cards, EDN, Nov. 23, 1995, pp. 34-42, the entire disclosure of which is hereby incorporated by reference.

It is a great challenge to design a high density, small chip size, low cost smart card integrated circuit. Such devices have many inherent problems. For example, chip sizes larger than 25 mm2 are prone to experiencing fractures when a card is flexed.
Additionally, at least with respect to logic devices, it is recognized in the art that the need for ever increasing performance has driven a migration from bulk substrates to other substrates such as semiconductor-on-insulator substrates (e.g., silicon-on-insulator or SOI substrates, silicon-on-glass substrates or silicon-on-sapphire substrates). For example, CMOS logic circuits disposed (e.g. formed) on SOI substrates may realize performance increases of 30% over bulk counterparts using the same design groundrules. Logic circuitry which supports various types of memory also benefits from these performance increases by providing higher bandwidth between the logic circuitry and the memory elements. These logic devices include, but are not limited to, CMOS and bipolar devices.
The present inventors believe that migration to other than bulk substrates will benefit memory elements. Therefore, this invention covers new memory structures (i.e. NVRAM, SRAM, DRAM structures) formed on substrates other than bulk substrates, such as SOI substrates. Increased performance from the logic circuitry can then likely be realized.
With reference to FIG. 1A, there is shown a conventional SOI wafer or SOI substrate. The wafer, which may be formed by SIMOX or bonding methods well known in the art, includes a base layer A2, an insulating layer A3 and an SOI layer A1. See, for example, U.S. Pat. Nos. 5,656,537, 5,646,053 which are hereby incorporated in their entireties by reference. The base layer, provided primarily for structural support, is typically a semiconductor, preferably silicon. The insulating layer is normally silicon dioxide and is approximately 60-500 nm thick. The insulating layer alternatively comprises silicon nitride, phosphosilicate glass, borophosphosilicate glass or composite layers of silicon dioxide, silicon nitride, phosphosilicate glass, and/or borophosphosilicate glass. The SOI layer A1, which is approximately 50-500 nm thick, is typically silicon, but can alternatively be silicon-germanium. The SOI layer A1 has been heat treated. In the case of an SOI wafer formed by a SIMOX method as mentioned herein above, the heat treatment serves to repair any defects created therein during preceding processing steps. In the case of an SOI wafer formed by a bonding method, the heat treatment serves to promote bonding of the two substrates.
The present invention seeks to overcome the above problems as well as others by providing new memory structures and methods for making the structures.
The inventors realized that it would be very desirable to replace the fuses described above with EEPROM cells, or nonvolatile memory. However, they also realized the difficulties in combining processes for forming different types of memory cells on the same substrate. Known processes for combining different types of memory cells involve many complex process steps, many extra masking levels and material layers to fabricate more than one type of memory cell on a single chip. Such processes are time consuming and costly. An alternative approach integrated memory cells only on a system level, rather than on the same chip.
The present invention provides a solution to the above by providing compatible memory cell structures and processes for forming different memory cell structure types on a single substrate other than a bulk substrate, such as a semiconductor-on-insulator (SOI) substrate.
The present invention also provides a new NVRAM cell structure.
According to preferred aspects, the present invention provides a semiconductor memory device including an NVRAM cell structure, a DRAM cell structure, and an SRAM cell structure on a single substrate other than a bulk substrate, such as a semiconductor-on-insulator substrate.
According to additional preferred aspects, the present invention provides a new NVRAM cell structure that includes an extended planarized floating gate.
According to other preferred aspects, the present invention provides processes for forming a semiconductor memory device including an NVRAM cell structure, a DRAM cell structure, and an SRAM cell structure on the same semiconductor-on-insulator substrate and associated with a plurality of gate structures, including first polysilicon layers. The method includes depositing a second polysilicon layer over the gate structures. A floating gate of an NVRAM cell is formed by patterning the second layer of polysilicon over at least a stud interconnection connected to one of said gate structures on said substrate and associated with a first drain region and a first source region in the substrate. A capacitor of a DRAM cell or an SRAM cell is formed by patterning the second layer of polysilicon over at least a second drain region formed in the substrate. A thin layer of a dielectric is deposited over exposed surfaces of the patterned second polysilicon layer. A third layer of polysilicon is deposited on the patterned second polysilicon layer. A control gate of the NVRAM cell is formed by patterning the third polysilicon layer over the dielectric layer deposited on corresponding patterned portions of the second polysilicon layer. A ground plate of the DRAM cell or the body of a Thin-Film Transistor(TFT) SRAM cell is formed by patterning the third polysilicon layer over the dielectric layer deposited on corresponding patterned portions of the second polysilicon layer.
Furthermore, preferred aspects of the present invention also include an semiconductor memory device formed according to the above process.
Still other objects and advantages of the present invention will become readily apparent to those skilled in the art from the following description. The detailed description shows and describes on preferred embodiments of the invention so as to illustrate the best mode contemplated for carrying out the invention. As those skilled in art will realize, the invention includes other and different embodiments. Details of the invention may be modified in various respects, without departing from the invention. Accordingly, the drawings and description should be regarded as illustrative in nature rather than restrictive.